* Explain the working of a MOSFET.
* Design an inverter with equal rise and fall time (given electron mobility = 2.5 times hole mobility).
* Draw the DC characteristics curve of an Inverter and show the effect of change in Aspect ratio on the curve.
* Design 2-input NAND and NOR gates with equal rise and fall time (given electron mobility = 2.5 times hole mobility).
* Draw layout of 2-input NAND and NOR gates.
* What is body-effect?
* Why NAND is preferred over NOR. (Hint: read sizing concepts).
* What are the limitations in increasing the voltage to reduce delay? (Hint: Power Dissipation).
* Why the size of VIA and contact is fixed? (Hint:Contact Spiking limits the size.)
* How do you draw a layout of CMOS circuit with unusual size, e.g. 20000/0.18 um. (Hint: Fingering concept).
* What is charge sharing?
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* Give CMOS implementation of boolean function F = AB+C.
* What happens if we flip NMOS and PMOS from the inverter, does it acts as a buffer?
* What is the difference between Testing & Verification?
* What is the basic difference between a latch and a flip-flop?
* What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
* If you increase the output load, would gate delay increase or decrease? why?
* How skew is goint to effect your setup and hold? Will it help the setup?
* If skew is more, how it is going to effect your design?
*How we will decide the path as a false path? Can you tell by taking mux as an example?
* Why do we fix hold violations only after Clock Tree Synthesis?
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